1. Field of the Invention
This invention relates generally to the field of semiconductor memory and logic devices. The invention relates more specifically to a method of fabricating a semiconductor multilevel interconnect structure, as well as the resulting structure.
2. Description of the Related Art
In order to improve the speed of semiconductor devices on integrated circuits, it has become desirable to use conductive materials, such as copper, having low resistivity and low k (a dielectric constant of less than 4.0) in order to reduce the capacitive coupling between structures such as interconnect lines.
Because materials such as copper are difficult to etch in a precise pattern, a method of fabrication known as a dual damascene process can be used to form the interconnects. In a conventional dual damascene process, a dielectric layer is etched to define both the contacts and vias, and the interconnect lines. Metal is then inlaid into the defined pattern and any excess metal is removed from the top of the structure in a planarization process, such as chemical mechanical polishing.
In order to provide the interconnects such as those fabricated from copper, various approaches have been proposed. For example, photolithography using an SiO2/SiNx dual hardmask for an organic low k dual damascene process is known. In another approach, described in U.S. Pat. No. 6,291,334, a low k etch stop material, such as an amorphous carbon, is deposited between two dielectric layers and is then patterned to define the underlying interlevel contacts/vias. The entire dual damascene structure is then etched in a single selective etch process which first etches the patterned interconnects, then etches the contact/vias past the patterned etch stop. The etch stop has a low dielectric constant relative to a conventional SiN etch stop, thereby minimizing the capacitive coupling between adjacent interconnect lines.
In still another approach, described in U.S. Pat. No. 6,297,554, a dual damascene process is employed to produce a structure having at least one trench in the surface of a dielectric layer, an insulating layer in the trench, and at least one void in the insulating layer. The insulating layer can consist of a low dielectric constant material such as amorphous carbon. The void is used to reduce the effective dielectric constant of the dielectric layer so as to reduce the parasitic capacitance between two adjacent copper wiring lines.
Despite the benefits of using interconnects such as those fabricated from copper, there can be certain drawbacks associated with use of a conventional dual damascene process. First, the conventional process can leave an undesirable “ear” (or “fence” or “fender”) formation of photoresist residue at the trench/via edge. FIG. 6 is a partial cross-sectional view of a structure 300 fabricated by a conventional dual damascene process. Once the bulk of the photoresist has been removed, a residue of photoresist 340 may still be left on intermetal dielectric layer (IMD) 310 at each of the trench 330/via 320 edges. The presence of the photoresist residue can adversely affect the performance of the multilevel interconnect.
Secondly, one of the major problems associated with dual damascene integration, especially when a low k IMD layer is used, is the “poisoning” of the IMD which can result from the interaction between the photoresist and the IMD. The poisoning, which occurs during application of the photoresist, arises because a low k IMD material, which is relatively porous, can absorb chemicals associated with the photoresist. The subsequent outgassing of these chemicals during via metallization leads to structural defects in the via. Neither of the above-described conventional dual damascene processes overcomes either of these drawbacks.
Thirdly, another drawback associated with conventional dual damascene processes is their lack of flexibility. For example, with the conventional process, the IMD may be partially etched before the trench and/or via patterning are completed. If there is any misalignment in the trench/via patterning, it cannot be corrected once the IMD has been etched.
Finally, in conventional dual damascene processes, the photoresist is optimized not for imaging performance, but rather, for its etch resistance. That is, because the photoresist must be etch resistant (i.e., relatively thick) in a conventional process, the imaging qualities of the photoresist may be compromised for the benefit of etch performance.
Therefore, a need exists for a method of dual damascene fabrication which not only avoids the formation of residual photoresist and avoids poisoning of the IMD, but which provides flexibility in patterning and provides for optimization of the photoresist for imaging performance.